Supercapacitor Auto Balancing (SABTM) MOSFET

 
The principle behind the Supercap Auto Balancing MOSFET in balancing supercaps is quite simple. It is based on the natural threshold characteristics of a MOSFET device. The threshold voltage of a MOSFET is the voltage at which a MOSFET turns on and starts to conduct a current. The drain current of the MOSFET, at or below its threshold voltage, is an exponentially non-linear function of its gate voltage. Hence, for small changes in the MOSFET's gate voltage, its on-current can vary greatly, by orders of magnitude. ALD's SAB MOSFETs take advantage of this basic characteristic.

SAB MOSFETs can be connected in parallel or in a series, to suit the desired leakage current characteristics, in order to charge-balance an array of supercaps. The combined SAB MOSFET and supercap array is designed to be self-regulating with various supercap array leakage mismatches and environmental temperature changes. The SAB MOSFETs can also be used only in the subthreshold mode, meaning the SAB MOSFET is used entirely at min., nominal and max. operating voltages in voltage ranges below its specified threshold voltage.

For the ALD8100xx/ALD9100xx family of SAB MOSFETs, the threshold voltage Vt of a SAB MOSFET is defined as its drain-gate source voltage at a drain-source ON current, IDS(ON) = 1µA when its gate and drain terminals are connected together (VGS = VDS). This voltage is specified as xx, where the threshold voltage is in 0.10V increments. For example, the ALD810025 features a 2.50V threshold voltage MOSFET with drain-gate source voltage, Vt = 2.50V, and IDS(ON) = 1µA. The SAB MOSFET has a precision trimmed threshold voltage where the tolerance of the threshold voltage is very tight, typically 2.50V +/-0.005V. When a 2.50V drain-gate source voltage bias is applied across an ALD810025/ALD910025 SAB MOSFET, it conducts an IDS(ON) = 1µA.

As all ALD8100xx and ALD9100xx devices operate the same way, an ALD810025 is used in the following illustration. At voltages below its threshold voltage, the ALD810025 rapidly turns off at a rate of approximately one decade of current per 104mV of voltage drop. Hence, at VGS = VDS = 2.396V, the ALD810025 has drain current of 0.1µA. At VGS = VDS = 2.292V, the ALD810025 drain current becomes 0.01µA. At VGS = VDS = 2.188V, the drain current is 0.001µA. It is apparent that at VGS = VDS ≤ 2.10V, the drain leakage current ≤ 0.00014µA, which is essentially zero when compared to 1µA initial threshold current. When individual VGS = VDS voltages fall below 1.9V, the SAB MOSFET leakage current essentially goes to zero (~70pA).

This exponential relationship between the Drain-Gate Source Voltage and the Drain-Source ON Current is an important consideration for replacing certain supercap charge balancing applications currently using fixed resistor or operational amplifier charge balancing. These other conventional charge-balancing circuits would continue to dissipate a significant amount of current, even after the voltage across the supercaps had dropped, because the current dissipated is a linear function, rather than an exponential function, of the supercap voltage (I = V/R). For supercap stacks consisting of more than two supercaps, the challenge of supercap balancing becomes more onerous.

For other IC circuits that offer charge balancing, active power is still being consumed even if the supercap voltage falls below 2.0V. For a four-cell supercap stack, this translates into a 2.0V x 4 ~= 8.0V power supply for an IC charge-balancing circuit. Even a two-cell supercap stack would be operating such an IC circuit with 2.0V x 2 = 4V. A supercap stack with SAB MOSFET charge-balancing, on the other hand, would be the only way to lose exponentially decreasing amount of charge with time and preserve by far the greatest amount of charge on each of the supercaps, by not adding charge loss to the leakages contributed by the supercaps themselves.

At VGS = VDS voltages of the ALD810025 above its Vt threshold voltage, its drain current behavior has the opposite near-exponential effect. At VGS = VDS = 2.60V, for example, the ALD810025 IDS(ON) increases tenfold to 10µA. Similarly, IDS(ON) becomes 100µA for a VGS = VDS voltage increase to 2.74V, and 300µA at 2.84V. (See Table 1)

As IDS(ON) changes rapidly with applied voltage on the Drain-Gate to Source pins, the SAB MOSFET device acts like a voltage limiting regulator with self-adjusting current levels. When this SAB MOSFET is connected across a supercap cell, the total leakage current across the supercap is compensated and corrected by the SAB MOSFET.

Consider the case when two supercap cells are connected in series, each with a SAB MOSFET connected across it in the Vt mode (VGS = VDS), charged by a power supply to a voltage equal to 2 x VS.

If the top supercap has a higher internal leakage current than the bottom supercap, the voltage VS(top) across it tends to drop lower than that of the bottom supercap. The SAB MOSFET IDS(ON) across the top supercap, sensing this voltage drop, drops off rapidly. Meanwhile, the bottom supercap VS(bottom) voltage tends to rise, as VS(bottom) = (2 x VS) - VS(top). This tendency for the voltage rise also increases VGS = VDS voltage of the SAB MOSFET across the bottom supercap. This increased VGS = VDS voltage would cause the IDS(ON) current of the bottom SAB MOSFET to increase rapidly as well. The excess leakage current of the top supercap would now leak across the bottom SAB MOSFET, reducing the voltage rise tendency of the lower supercap. With this self-regulating mechanism, the top supercap, VS(top), voltage tends to rise while the bottom supercap, VS(bottom), voltage tends to drop, creating simultaneously opposing actions of the supercap leakage currents.

With appropriate design and selection of a specific SAB MOSFET device for a given pair of supercaps, it is now possible to have regulation and balancing of two series-connected supercaps, at essentially no extra leakage current, since the SAB MOSFET only conducts the difference in leakage current between the two supercaps.

Likewise, the case of the bottom supercap having a higher leakage current than that of the top supercap works in similar fashion, with the tendency of the bottom supercap, VS(bottom), voltage to drop, compensated by the tendency of the top supercap, VS(top), voltage to drop as well, effected by the top SAB MOSFET. This SAB MOSFET charge balancing scheme also extends to up to four supercaps in a series network by using four SAB MOSFETs in a single ALD8100xx SAB MOSFET package.

As ambient temperature increases, the supercap leakage current, as a function of temperature, increases. The SAB MOSFET threshold voltage is reduced with temperature increase, which causes the drain current to increase with temperature as well. This drain current increase compensates for the leakage current increase within the supercap, reducing the overall supercap temperature leakage effect and preserving charge balancing effectiveness. This temperature compensation assumes that all the supercaps and the SAB MOSFETs are in the same temperature environments.

Each drain pin of a SAB MOSFET has an internal reverse biased diode to its source pin, which can become forward biased if the drain voltage should become negative relative to its source pin. This forward-biased diode clamps the drain voltage to limit the negative voltage relative to its source voltage, and is limited to 80mA max. rated current between any two pins.

Learn about ALD's new selection of PCBs with mounted SAB MOSFETS.

Read about ALD's Plug-and-Play Supercapacitor Balancing Solution Using PC Boards.